A new type of hafnium-based ferroelectric memory chip developed and designed by Liu Ming, Academician of the Institute of Microelectronics, has been presented at the IEEE International Solid-State Circuits Conference (ISSCC) in 2023, the highest level of integrated circuit design.
High-performance embedded non-volatile memory (eNVM) is in high demand for SOC chips in consumer electronics, autonomous vehicles, industrial control and edge devices for the Internet of Things. Ferroelectric memory (FeRAM) has the advantages of high reliability, ultra-low power consumption, and high speed. It is widely used in large amounts of data recording in real time, frequent data reading and writing, low power consumption and embedded SoC/SiP products. Ferroelectric memory based on PZT material has achieved mass production, but its material is incompatible with CMOS technology and difficult to shrink, leading to the development process of traditional ferroelectric memory is seriously hindered, and embedded integration needs a separate production line support, difficult to popularize on a large scale. The miniaturability of new hafnium-based ferroelectric memory and its compatibility with CMOS technology make it a research hotspot of common concern in academia and industry. Hafnium-based ferroelectric memory has been regarded as an important development direction of the next generation of new memory. At present, the research of hafnium-based ferroelectric memory still has problems such as insufficient unit reliability, lack of chip design with complete peripheral circuit, and further verification of chip level performance, which limits its application in eNVM.
Aiming at the challenges faced by embedded hafnium-based ferroelectric memory, the team of Academician Liu Ming from the Institute of Microelectronics has designed and implemented the megab-magnitude FeRAM test chip for the first time in the world based on the large-scale integration platform of hafnium-based ferroelectric memory compatible with CMOS, and successfully completed the large-scale integration of HZO ferroelectric capacitor in 130nm CMOS process. An ECC-assisted write drive circuit for temperature sensing and a sensitive amplifier circuit for automatic offset elimination are proposed, and 1012 cycle durability and 7ns write and 5ns read time are achieved, which are the best levels reported so far.
The paper “A 9-Mb HZO-based Embedded FeRAM with 1012-Cycle Endurance and 5/7ns Read/Write using ECC-Assisted Data Refresh” is based on the results and Offset-Canceled Sense Amplifier “was selected in ISSCC 2023, and the chip was selected in the ISSCC Demo Session to be displayed in the conference. Yang Jianguo is the first author of the paper, and Liu Ming is the corresponding author.
The related work is supported by the National Natural Science Foundation of China, the National Key Research and Development Program of the Ministry of Science and Technology, and the B-Class Pilot Project of the Chinese Academy of Sciences.
(Photo of 9Mb Hafnium-based FeRAM chip and chip performance test)
Post time: Apr-15-2023
