The high threshold of chip design is being “crushed” by AI

In the past few years, the chip industry has seen some interesting changes in market competition. the PC processor market, the long-standing dominant Intel faces a fierce attack from AMD. In the cell phone processor market, Qualcomm has given up the number one spot in shipments for five consecutive quarters, and MediaTek is in full swing.

When the traditional chip giants competition intensified, technology giants who are good at software and algorithms have started to develop their own chips, making the chip industry competition more interesting.

Behind these changes, on the one hand, because Moore's Law slowed down after 2005, more importantly, the rapid development of digital brought about by the demand for differentiation.

Chip giants provide general-purpose chip performance is certainly reliable, and the increasingly large and diverse application needs of autonomous driving, high-performance computing, AI, etc., in addition to the performance of the pursuit of more differentiated features, technology giants had to start their own chip research to consolidate their ability to grasp the end market.

While the competitive landscape of the chip market changes, we can see that the chip industry will usher in greater change, the factors driving all this change is the very hot AI in recent years.

Some industry experts say that AI technology will bring disruptive changes to the entire chip industry. Wang Bingda, chief innovation officer of Synopsys, head of AI lab and vice president of global strategic project management, told Thunderbird, "If it is said that the chip is designed with EDA (Electronic Design Automation) tools that introduce AI technology, I agree with this statement."

If AI is applied to individual aspects of chip design, it can integrate the accumulation of experienced engineers into EDA tools and significantly reduce the threshold of chip design. If AI is applied to the entire process of chip design, the same experience can be used to optimize the design process, significantly shorten the chip design cycle while improving chip performance and reducing design