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STM32G0B1CEU6 ARM Microcontrollers – MCU Mainstream Arm Cortex-M0+ 32-bit MCU, up to 512KB Flash, 144KB RAM, 6x USART

STM32G0B1CEU6 ARM Microcontrollers – MCU Mainstream Arm Cortex-M0+ 32-bit MCU, up to 512KB Flash, 144KB RAM, 6x USART Featured Image
  • STM32G0B1CEU6 ARM Microcontrollers – MCU Mainstream Arm Cortex-M0+ 32-bit MCU, up to 512KB Flash, 144KB RAM, 6x USART

Short Description:

Manufacturers: STMicroelectronics
Product Category: ARM Microcontrollers – MCU
Data Sheet: STM32G0B1CEU6
Description:Microcontrollers – MCU
RoHS status: RoHS Compliant


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Product Detail

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Product Tags

♠ Product Description

Product Attribute Attribute Value
Manufacturer: STMicroelectronics
Product Category: ARM Microcontrollers - MCU
RoHS:  Details
Series: STM32G0
Mounting Style: SMD/SMT
Core: ARM Cortex M0+
Program Memory Size: 512 kB
Data Bus Width: 32 bit
ADC Resolution: 12 bit
Maximum Clock Frequency: 64 MHz
Number of I/Os: 44 I/O
Data RAM Size: 144 kB
Supply Voltage - Min: 1.7 V
Supply Voltage - Max: 3.6 V
Minimum Operating Temperature: - 40 C
Maximum Operating Temperature: + 85 C
Packaging: Tray
Brand: STMicroelectronics
Interface Type: UART
Moisture Sensitive: Yes
Product Type: ARM Microcontrollers - MCU
Factory Pack Quantity: 1560
Subcategory: Microcontrollers - MCU
Tradename: STM32
Unit Weight: 0.003527 oz

♠ Multiprotocol wireless 32-bit MCU Arm®-based Cortex®-M4 with FPU, Bluetooth® 5.2 radio solution

The STM32WB15CC multiprotocol wireless and ultra-low-power device embeds a powerful and ultra-low-power radio compliant with the Bluetooth® Low Energy SIG specification 5.2. It contains a dedicated Arm® Cortex®-M0+ for performing all the real-time low layer operation.

The device is designed to be extremely low-power and is based on the high-performance Arm® Cortex®-M4 32-bit RISC core operating at a frequency of up to 64 MHz. This core features a Floating point unit (FPU) single precision that supports all Arm® single-precision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) that enhances application security.

Enhanced inter-processor communication is provided by the IPCC with six bidirectional channels. The HSEM provides hardware semaphores used to share common resources between the two processors.

The device embeds high-speed memories (320 Kbytes of Flash memory, 48 Kbytes of SRAM) and an extensive range of enhanced I/Os and peripherals.

Direct data transfer between memory and peripherals and from memory to memory is supported by seven DMA channels with a full flexible channel mapping by the DMAMUX peripheral.

The device feature several mechanisms for embedded Flash memory and SRAM: readout protection, write protection and proprietary code readout protection. Portions of the memory can be secured for Cortex® -M0+ exclusive access.


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  • •  Includes ST state-of-the-art patented technology 

    •  Radio

      – 2.4 GHz – RF transceiver supporting Bluetooth® 5.2 specification

      – RX sensitivity: -95.5 dBm (Bluetooth® Low Energy at 1 Mbps)

      – Programmable output power up to +5.5 dBm with 1 dB steps

      – Integrated balun to reduce BOM

      – Support for 2 Mbps

      – Dedicated Arm® 32-bit Cortex® M0+ CPU for real-time Radio layer

      – Accurate RSSI to enable power control

      – Suitable for systems requiring compliance with radio frequency regulations ETSI EN 300 328, EN 300 440, FCC CFR47 Part 15 and ARIB STD-T66

      – Support for external PA

      – Available integrated passive device (IPD) companion chip for optimized matching solution (MLPF-WB-01E3) 

    •  Ultra-low-power platform

      – 1.71 to 3.6 V power supply

      – – 40 °C to 85 / 105 °C temperature ranges

      – 12 nA shutdown mode

      – 610 nA Standby mode + RTC + 48 KB RAM

      – Active-mode MCU: 33 µA / MHz when RF and SMPS on

      – Radio: Rx 4.5 mA / Tx at 0 dBm 5.2 mA 

    •  Core: Arm® 32-bit Cortex®-M4 CPU with FPU, adaptive real-time accelerator (ART Accelerator) allowing 0-wait-state execution from Flash memory, frequency up to 64 MHz, MPU, 80 DMIPS and DSP instructions 

    •  Performance benchmark

      – 1.25 DMIPS/MHz (Drystone 2.1) 

    •  Supply and reset management

      – High efficiency embedded SMPS step-down converter with intelligent bypass mode

      – Ultra-safe, low-power BOR (brownout reset) with five selectable thresholds

      – Ultra-low-power POR/PDR

      – Programmable voltage detector (PVD)

      – VBAT mode with RTC and backup registers 

    •  Clock sources

      – 32 MHz crystal oscillator with integrated trimming capacitors (Radio and CPU clock)

      – 32 kHz crystal oscillator for RTC (LSE)

      – Internal low-power 32 kHz RC (LSI1)

      – Internal low-drift 32 kHz RC (LSI2)

      – Internal multispeed 100 kHz to 48 MHz oscillator, factory-trimmed

      – High speed internal 16 MHz factory trimmed RC

      – 1x PLL for system clock and ADC 

    •  Memories

      – 320 KB Flash memory with sector protection (PCROP) against R/W operations, enabling radio stack and application

      – 48 KB SRAM, including 36 KB with hardware parity check

      – 20×32-bit backup register

      – Boot loader supporting USART, SPI, I2C interfaces

      – 1 Kbyte (128 double words) OTP

    •  Rich analog peripherals (down to 1.62 V)

      – 12-bit ADC 2.5 Msps, 190 µA/Msps

      – 1x ultra-low-power comparator 

    •  System peripherals

      – Inter processor communication controller (IPCC) for communication with Bluetooth® Low Energy

      – HW semaphores for resources sharing between CPUs

      – 1x DMA controller (7x channels) supporting ADC, SPI, I2C, USART, AES, timers

      – 1x USART (ISO 7816, IrDA, SPI Master, Modbus and Smartcard mode)

      – 1x LPUART (low power)

      – 1x SPI 32 Mbit/s

      – 1x I2C (SMBus/PMBus®)

      – Touch sensing controller, up to eight sensors

      – 1x 16-bit, four channels advanced timer

      – 1x 32-bit, four channels timer

      – 2x 16-bit ultra-low-power timer

      – 1x independent Systick

      – 1x independent watchdog

      – 1x window watchdog

    •  Security and ID

      – Secure firmware installation (SFI) for Bluetooth® Low Energy SW stack

      – 2x hardware encryption AES maximum 256-bit for the application and the Bluetooth® Low Energy

      – HW public key authority (PKA)

      – Cryptographic algorithms: RSA, Diffie-Helman, ECC over GF(p)

      – True random number generator (RNG)

      – Sector protection against R/W operation (PCROP)

      – CRC calculation unit – Die information: 96-bit unique ID

      – IEEE 64-bit unique ID. Possibility to derive Bluetooth® Low Energy 48-bit EUI 

    •  Up to 37 fast I/Os, 35 of them 5 V-tolerant 

    •  Development support

      – Serial wire debug (SWD), JTAG for the application processor

      – Application cross trigger

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