P1020NXN2HFB Microprocessors – MPU 800/400/667 ET NE r1.1
♠ Product Description
| Product Attribute | Attribute Value |
| Manufacturer: | NXP |
| Product Category: | Microprocessors - MPU |
| RoHS: | Details |
| Mounting Style: | SMD/SMT |
| Package/Case: | TEPBGA-689 |
| Series: | P1020 |
| Core: | e500 |
| Number of Cores: | 2 Core |
| Data Bus Width: | 32 bit |
| Maximum Clock Frequency: | 800 MHz |
| L1 Cache Instruction Memory: | 2 x 32 kB |
| L1 Cache Data Memory: | 2 x 32 kB |
| Operating Supply Voltage: | 1 V |
| Minimum Operating Temperature: | - 40 C |
| Maximum Operating Temperature: | + 125 C |
| Packaging: | Tray |
| Brand: | NXP Semiconductors |
| I/O Voltage: | 1.5 V, 1.8 V, 2.5 V, 3.3 V |
| Instruction Type: | Floating Point |
| Interface Type: | Ethernet, I2C, PCIe, SPI, UART, USB |
| L2 Cache Instruction / Data Memory: | 256 kB |
| Memory Type: | L1/L2 Cache |
| Moisture Sensitive: | Yes |
| Number of I/Os: | 16 I/O |
| Processor Series: | QorIQ |
| Product Type: | Microprocessors - MPU |
| Factory Pack Quantity: | 27 |
| Subcategory: | Microprocessors - MPU |
| Tradename: | QorIQ |
| Watchdog Timers: | No Watchdog Timer |
| Part # Aliases: | 935310441557 |
| Unit Weight: | 5.247 g |
• Dual high-performance 32-bit cores, built on Power Architecture® technology:
– 36-bit physical addressing
– Double-precision floating-point support
– 32 Kbyte L1 instruction cache and 32 Kbyte L1 data cache for each core
– 533 MHz to 800 MHz clock frequency
• 256 Kbyte L2 cache with ECC. Also configurable as SRAM and stashing memory.
• Three 10/100/1000 Mbps enhanced three-speed Ethernet controllers (eTSECs)
– TCP/IP acceleration, quality of service, and classification capabilities
– IEEE® 1588 support
– Lossless flow control
– MII, RMII, RGMII, SGMII
• High-speed interfaces supporting various multiplexing options:
– Four SerDes upto 2.5 GHz/lane multiplexed across controllers
– Two PCI Express interfaces
– Two SGMII interfaces
• High-Speed USB controller (USB 2.0)
– Host and device support
– Enhanced host controller interface (EHCI)
– ULPI interface to PHY
• Enhanced secure digital host controller (SD/MMC)
• Enhanced Serial peripheral interface (eSPI)
• Integrated security engine
– Protocol support includes ARC4, 3DES, AES, RSA/ECC, RNG, single-pass SSL/TLS
– XOR acceleration
• 32-bit DDR2/DDR3 SDRAM memory controller with ECC support
• Programmable interrupt controller (PIC) compliant with OpenPIC standard
• One four-channel DMA controller
• Two I2 C controllers, DUART, timers
• Enhanced local bus controller (eLBC)
• TDM
• 16 general-purpose I/O signals
• Operating junction temperature (Tj ) range: 0–125°C and –40°C to 125°C (industrial specification)
• 31 × 31 mm 689-pin WB-TePBGA II (wire bond temperature-enhanced plastic BGA)
